João Paulo de Castro Canas Ferreira


AuthID: R-000-7A5

Confirmed Publications: 96



1
TITLE: Memory Optimization for FPGA Implementation of Correlation-Based Beamforming
AUTHORS: Helder Avelar; João Canas Ferreira ;
PUBLISHED: 2024, SOURCE: 22nd IEEE Mediterranean Electrotechnical Conference, MELECON 2024 in 2024 IEEE 22nd Mediterranean Electrotechnical Conference, MELECON 2024, VOLUME: 12
INDEXED IN: Scopus CrossRef
IN MY: ORCID
2
TITLE: A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA
AUTHORS: Sousa, Luis Miguel; Paulino, Nuno ; Ferreira, Joao Canas ; Bispo, Joao ;
PUBLISHED: 2022, SOURCE: 21st IEEE Mediterranean Electrotechnical Conference (IEEE MELECON) in 2022 IEEE 21ST MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (IEEE MELECON 2022), VOLUME: abs/2112.01875
INDEXED IN: Scopus WOS DBLP CrossRef: 2
IN MY: ORCID | DBLP
3
TITLE: A Binary Translation Framework for Automated Hardware Generation  Full Text
AUTHORS: Paulino, N ; Bispo, J ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2021, SOURCE: IEEE MICRO, VOLUME: 41, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 2
IN MY: ORCID | DBLP
4
TITLE: On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
AUTHORS: Santos, Tiago; Paulino, Nuno ; Bispo, Joao ; Cardoso, Joao M. P. ; Ferreira, Joao C. ;
PUBLISHED: 2021, SOURCE: 20th International Conference on Field-Programmable Technology (ICFPT) in 2021 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
5
TITLE: Pedagogical Innovation in Pandemic Times: The Experience of a Microprocessor Programming Course
AUTHORS: Lima, Bruno ; Granhao, Daniel ; Araujo, Antonio J. ; Ferreira, Joao Canas ;
PUBLISHED: 2021, SOURCE: 4th International Conference of the Portuguese-Society-for-Engineering-Education (CISPEE) in 2021 4TH INTERNATIONAL CONFERENCE OF THE PORTUGUESE SOCIETY FOR ENGINEERING EDUCATION (CISPEE)
INDEXED IN: Scopus WOS CrossRef Unpaywall
IN MY: ORCID
6
TITLE: Transparent Control Flow Transfer between CPU and Accelerators for HPC  Full Text
AUTHORS: Granhao, D ; Ferreira, JC ;
PUBLISHED: 2021, SOURCE: ELECTRONICS, VOLUME: 10, ISSUE: 4
INDEXED IN: Scopus WOS CrossRef: 1
IN MY: ORCID
7
TITLE: A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications  Full Text
AUTHORS: Ferreira, ML; Ferreira, JC ;
PUBLISHED: 2020, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 92, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID | DBLP
8
TITLE: A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems  Full Text
AUTHORS: Miyandoab, FD; Ferreira, JC ; Tavares, VMG ; da Silva, JM ; Fernando José Velez ;
PUBLISHED: 2020, SOURCE: IEEE-ACM TRANSACTIONS ON NETWORKING, VOLUME: 28, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef: 5 Handle
IN MY: ORCID | DBLP
9
TITLE: Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: 30th International Conference on Field-Programmable Logic and Applications (FPL) in 2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
10
TITLE: Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications
AUTHORS: Mário Lopes Ferreira; João Canas Ferreira ;
PUBLISHED: 2020, SOURCE: Field Programmable Gate Arrays (FPGAs) II
INDEXED IN: CrossRef
IN MY: ORCID
Page 1 of 10. Total results: 96.

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