João Paulo de Castro Canas Ferreira


AuthID: R-000-7A5

Confirmed Publications: 96



31
TITLE: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | ResearcherID | DBLP
32
TITLE: MICPRO DSD 2015 special issue  Full Text
AUTHORS: Joao Canas Ferreira ; Paris Kitsos;
PUBLISHED: 2017, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 52
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
33
TITLE: Towards a type 0 hypervisor for dynamic reconfigurable systems
AUTHORS: Benedikt Janßen; Fatih Korkmaz; Halil Derya; Michael Hübner; Mário Lopes Ferreira; João Canas Ferreira ;
PUBLISHED: 2017, SOURCE: International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017
INDEXED IN: DBLP
IN MY: ORCID | DBLP
34
TITLE: Towards a Type 0 Hypervisor for Dynamic Reconfigurable Systems
AUTHORS: Benedikt Janssen; Fatih Korkmaz; Halil Derya; Michael Huebner; Mario Lopes Ferreira ; Joao Canas Ferreira ;
PUBLISHED: 2017, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2017 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXED IN: WOS CrossRef: 4
IN MY: ORCID
35
36
TITLE: A small fully digital open-loop clock and data recovery circuit for wired BANs. A Small Fully Digital Open-Loop CDR Circuit for Wired BANs  Full Text
AUTHORS: Fardin Derogarian; Joao Canas Ferreira ; Vitor Grade Tavares ;
PUBLISHED: 2016, SOURCE: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, VOLUME: 44, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID | ResearcherID | DBLP
37
TITLE: An FPGA Implementation of a Long Short-Term Memory Neural Network
AUTHORS: Joao Canas Ferreira ; Jose Fonseca;
PUBLISHED: 2016, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16)
INDEXED IN: Scopus WOS DBLP CrossRef: 39
IN MY: ORCID | ResearcherID | DBLP
38
TITLE: Dynamically Reconfigurable FFT Processor for Flexible OFDM Baseband Processing
AUTHORS: Mario Lopes Ferreira ; Amin Barahimi ; Joao Canas C Ferreira ;
PUBLISHED: 2016, SOURCE: 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) in 2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS)
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | ResearcherID | DBLP
39
TITLE: Dynamically Reconfigurable LTE-compliant OFDM Modulator for Downlink Transmission
AUTHORS: Mario Lopes Ferreira ; Amin Barahimi ; Joao Canas Ferreira ;
PUBLISHED: 2016, SOURCE: 31st Conference on Design of Circuits and Integrated Systems (DCIS) in 2016 CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2016)
INDEXED IN: Scopus WOS CrossRef: 10
IN MY: ORCID | ResearcherID
40
TITLE: Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications
AUTHORS: Mário Lopes Ferreira ; Amin Barahimi ; João Canas Ferreira ;
PUBLISHED: 2016, SOURCE: 12th International Symposium on Applied Reconfigurable Computing, ARC 2016 in Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings, VOLUME: 9625
INDEXED IN: Scopus DBLP CrossRef: 11
IN MY: ORCID | ResearcherID | DBLP
Page 4 of 10. Total results: 96.

A place for researchers and their institutions

Useful Links

Get Help

© 2024 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service