José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 98



71
TITLE: Array hybrid multiplier versus modified booth multiplier: Comparing area and power consumption of layout implementations of signed radix-4 architectures
AUTHORS: de Oliveira, LL; Costa, E; Bampi, S; Baptista, J; Monteiro, J ;
PUBLISHED: 2004, SOURCE: 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004) in 2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, VOLUME: 2
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
72
TITLE: Power estimation using probability polynomials  Full Text
AUTHORS: Costa, J; Silveira, L. Miguel ; Devadas, S; Monteiro, J ;
PUBLISHED: 2004, SOURCE: DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, VOLUME: 9, ISSUE: 1
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
73
TITLE: Low power architectures for FFT and FIR dedicated datapaths
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems in PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3
INDEXED IN: WOS
74
TITLE: A new architecture for 2's complement Gray encoded array multiplier
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 15th Symposium on Integrated Circuits and Systems Design in 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS CrossRef: 7
IN MY: ORCID
75
TITLE: A new architecture for signed Radix-2(m) pure array multipliers  Full Text
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 20th IEEE International Conference on Computer Design in ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
76
TITLE: Implicit FSM decomposition applied to low-power design  Full Text
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 2002, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 10, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID
77
TITLE: Power efficient arithmetic operand encoding
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
IN MY: ResearcherID
78
TITLE: Power optimized Viterbi Decoder implementation throught architectural transforms
AUTHORS: Portela, J; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
IN MY: ResearcherID
79
TITLE: FSM decomposition by direct circuit manipulation applied to low power design
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 2000, SOURCE: 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID
80
TITLE: Integrating dynamic power management in the design flow
AUTHORS: Mota, A; Ferreira, N; Oliveira, A ; Monteiro, J ;
PUBLISHED: 2000, SOURCE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
INDEXED IN: WOS DBLP
Page 8 of 10. Total results: 98.

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