Nuno Miguel Cardanha Paulino


AuthID: R-002-RAV

Confirmed Publications: 37



21
TITLE: FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
AUTHORS: Silva, Pedro Filipe; Bispo, Joao ; Paulino, Nuno ;
PUBLISHED: 2021, SOURCE: 20th International Conference on Field-Programmable Technology (ICFPT) in 2021 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
22
TITLE: Multiple target tracking with interaction using an MCMC MRF Particle Filter
AUTHORS: Hélder F S Campos; Nuno Paulino ;
PUBLISHED: 2021, SOURCE: CoRR, VOLUME: abs/2111.13184
INDEXED IN: DBLP
IN MY: ORCID | DBLP
23
TITLE: On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
AUTHORS: Santos, Tiago; Paulino, Nuno ; Bispo, Joao ; Cardoso, Joao M. P. ; Ferreira, Joao C. ;
PUBLISHED: 2021, SOURCE: 20th International Conference on Field-Programmable Technology (ICFPT) in 2021 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
24
TITLE: Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
AUTHORS: Paulino, N ; Ferreira, JC ; Bispo, J ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: 30th International Conference on Field-Programmable Logic and Applications (FPL) in 2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
25
TITLE: Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey  Full Text
AUTHORS: Nuno Paulin ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2020, SOURCE: ACM COMPUTING SURVEYS, VOLUME: 53, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 9
IN MY: ORCID | DBLP | CIÊNCIAVITAE
26
TITLE: Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
AUTHORS: Paulino, N ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | DBLP | CIÊNCIAVITAE
27
TITLE: Dynamic Partial Reconfiguration of Customized Single-Row Accelerators  Full Text
AUTHORS: Paulino, NMC ; Ferreira, JC ; Cardoso, JMP ;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 7
IN MY: ORCID | DBLP | CIÊNCIAVITAE
28
TITLE: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef: 6
IN MY: ORCID | DBLP | CIÊNCIAVITAE
29
TITLE: On Coding Techniques for Targeting FPGAs via OpenCL
AUTHORS: Nuno Paulino ; Luís Reis; João M P Cardoso ;
PUBLISHED: 2017, SOURCE: Parallel Computing is Everywhere, Proceedings of the International Conference on Parallel Computing, ParCo 2017, 12-15 September 2017, Bologna, Italy, VOLUME: 32
INDEXED IN: Scopus DBLP
IN MY: ORCID | DBLP | CIÊNCIAVITAE
30
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