Leonel Augusto Pires Seabra Sousa


AuthID: R-000-93B

Confirmed Publications: 283



261
TITLE: Insertion of irregular-shaped logos in the compressed DCT domain
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2002, SOURCE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 1
INDEXED IN: Scopus WOS CrossRef
262
TITLE: Video coding by using the 3D zero-tree approach in the wavelet transform domain
AUTHORS: Salvado, J; Sousa, L ;
PUBLISHED: 2002, SOURCE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 2
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
263
TITLE: A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
AUTHORS: Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2001, SOURCE: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, VOLUME: 218
INDEXED IN: DBLP CrossRef
IN MY: DBLP
264
TITLE: A platform independent parallelising tool based on graph theoretic models
AUTHORS: Sinnen, O; Sousa, L ;
PUBLISHED: 2001, SOURCE: 4th International Conference on Vector and Parallel Processing (VECPAR 2000) in VECTOR AND PARALLEL PROCESSING - VECPAR 2000, VOLUME: 1981
INDEXED IN: WOS
265
TITLE: Comparison of contention aware list scheduling heuristics for cluster computing
AUTHORS: Sinnen, O; Sousa, L ;
PUBLISHED: 2001, SOURCE: 30th International Conference on Parallel Processing (ICPP Workshops) in INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, PROCEEDINGS, VOLUME: 2001-January
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID | DBLP
266
TITLE: Exploiting Unused Time Slots in List Scheduling Considering Communication Contention
AUTHORS: Oliver Sinnen; Leonel Sousa ;
PUBLISHED: 2001, SOURCE: Euro-Par 2001: Parallel Processing, 7th International Euro-Par Conference Manchester, UK August 28-31, 2001, Proceedings, VOLUME: 2150
INDEXED IN: DBLP CrossRef
IN MY: DBLP
267
TITLE: Parameterizable hardware architectures for automatic synthesis of motion estimation processors
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2001, SOURCE: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01) in SIPS 2001: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
268
TITLE: Scheduling task graphs on arbitrary processor architectures considering contention
AUTHORS: Sinnen, O; Sousa, L ;
PUBLISHED: 2001, SOURCE: 9th International Conference on High-Performance Computing and Networking in HIGH-PERFORMANCE COMPUTING AND NETWORKING, VOLUME: 2110
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID | DBLP
269
TITLE: Synchronous non-local image processing on Orthogonal Multiprocessor Systems
AUTHORS: Sousa, L ; Sinnen, O;
PUBLISHED: 2001, SOURCE: 4th International Conference on Vector and Parallel Processing (VECPAR 2000) in VECTOR AND PARALLEL PROCESSING - VECPAR 2000, VOLUME: 1981
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID
270
TITLE: A Platform Independent Parallelising Tool Based on Graph Theoretic Models
AUTHORS: Oliver Sinnen; Leonel Sousa ;
PUBLISHED: 2000, SOURCE: Vector and Parallel Processing - VECPAR 2000, 4th International Conference, Porto, Portugal, June 21-23, 2000, Selected Papers and Invited Talks, VOLUME: 1981
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | DBLP
Page 27 of 29. Total results: 283.

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