Mário Pereira Véstias
AuthID: R-000-CZ3
31
TITLE: Efficient Design of Pruned Convolutional Neural Networks on FPGA Full Text
AUTHORS: Mario Vestias;
PUBLISHED: 2020, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
AUTHORS: Mario Vestias;
PUBLISHED: 2020, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
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ORCID32
TITLE: High-Speed Viterbi Decoder
AUTHORS: Vestias, MP;
PUBLISHED: 2020, SOURCE: Encyclopedia of Information Science and Technology, Fifth Edition
AUTHORS: Vestias, MP;
PUBLISHED: 2020, SOURCE: Encyclopedia of Information Science and Technology, Fifth Edition
33
TITLE: Field-Programmable Gate Array
AUTHORS: Véstias, MP;
PUBLISHED: 2020, SOURCE: Encyclopedia of Information Science and Technology, Fifth Edition
AUTHORS: Véstias, MP;
PUBLISHED: 2020, SOURCE: Encyclopedia of Information Science and Technology, Fifth Edition
34
TITLE: Deep Learning on Edge. Challenges and Trends
AUTHORS: Mário P Véstias;
PUBLISHED: 2020, SOURCE: Advances in Computational Intelligence and Robotics - Smart Systems Design, Applications, and Challenges
AUTHORS: Mário P Véstias;
PUBLISHED: 2020, SOURCE: Advances in Computational Intelligence and Robotics - Smart Systems Design, Applications, and Challenges
35
TITLE: Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning
AUTHORS: Peres, T; Gonçalves, A; Véstias, M;
PUBLISHED: 2019, SOURCE: 15th International Symposium on Applied Reconfigurable Computing, ARC 2019 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 11444 LNCS
AUTHORS: Peres, T; Gonçalves, A; Véstias, M;
PUBLISHED: 2019, SOURCE: 15th International Symposium on Applied Reconfigurable Computing, ARC 2019 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 11444 LNCS
36
TITLE: Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs
AUTHORS: Gonçalves, A; Peres, T; Véstias, M;
PUBLISHED: 2019, SOURCE: 15th International Symposium on Applied Reconfigurable Computing, ARC 2019 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 11444 LNCS
AUTHORS: Gonçalves, A; Peres, T; Véstias, M;
PUBLISHED: 2019, SOURCE: 15th International Symposium on Applied Reconfigurable Computing, ARC 2019 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 11444 LNCS
37
TITLE: Low energy heterogeneous computing with multiple RISC-V and CGRA cores
AUTHORS: Fiolhais, L; Gonçalves, F; Duarte, RP; Véstias, M; De Sousa, JT;
PUBLISHED: 2019, SOURCE: 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 2019-May
AUTHORS: Fiolhais, L; Gonçalves, F; Duarte, RP; Véstias, M; De Sousa, JT;
PUBLISHED: 2019, SOURCE: 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 2019-May
38
TITLE: A survey of convolutional neural networks on edge with reconfigurable computing
AUTHORS: Véstias, MP;
PUBLISHED: 2019, SOURCE: Algorithms, VOLUME: 12, ISSUE: 8
AUTHORS: Véstias, MP;
PUBLISHED: 2019, SOURCE: Algorithms, VOLUME: 12, ISSUE: 8
39
TITLE: A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing
AUTHORS: Vestias, MP;
PUBLISHED: 2019, SOURCE: ALGORITHMS, VOLUME: 12, ISSUE: 8
AUTHORS: Vestias, MP;
PUBLISHED: 2019, SOURCE: ALGORITHMS, VOLUME: 12, ISSUE: 8
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ORCID40
TITLE: Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores
AUTHORS: Fiolhais, L; Goncalves, F; Duarte, RP; Vestias, M; Sousa, JT;
PUBLISHED: 2019, SOURCE: IEEE International Symposium on Circuits and Systems (IEEE ISCAS) in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
AUTHORS: Fiolhais, L; Goncalves, F; Duarte, RP; Vestias, M; Sousa, JT;
PUBLISHED: 2019, SOURCE: IEEE International Symposium on Circuits and Systems (IEEE ISCAS) in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
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