51
TITLE: DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs
AUTHORS: Manuel G Gericota; Gustavo R Alves; Miguel L Silva; José M Ferreira;
PUBLISHED: 2001
INDEXED IN: Handle
52
TITLE: DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
AUTHORS: Manuel Gericota; Gustavo C Alves; Miguel L Silva; José M Ferreira;
PUBLISHED: 2001
INDEXED IN: Handle
53
TITLE: The RAT technique for concurrent test of dynamically reconfigurable hardware
AUTHORS: Manuel G Gericota; Gustavo R Alves; Ferreira, J. M. Martins;
PUBLISHED: 2000, SOURCE: XV Conference on Design of Circuits and Integrated Systems (DCIS’00)
INDEXED IN: Handle
54
TITLE: The RaT technique for concurrent test of dinamically reconfigurable hardware
AUTHORS: Manuel G Gericota; Gustavo R Alves; José M Ferreira;
PUBLISHED: 2000
INDEXED IN: Handle
55
TITLE: Building AAC systems to meet people needs
AUTHORS: Manuel Gericota; M. Lourenço; José M Ferreira;
PUBLISHED: 1996
INDEXED IN: Handle
57
TITLE: The Cost x Performance Tradeoff for Voice Output AAC Aids: Is It Real?
AUTHORS: José M Ferreira; Manuel Gericota; M. Lourenço;
PUBLISHED: 1995
INDEXED IN: Handle
58
TITLE: A VHDL library for MTM/BST communication
AUTHORS: Gustavo Alves; José A R Tavares; Manuel G Gericota; José M M Ferreira;
PUBLISHED: 1994
INDEXED IN: Handle
59
TITLE: Sistema Modular para o Teste de Cartas de Circuito Impresso com BST
AUTHORS: Gustavo R Alves; Manuel Gericota; Jose L Ramalho; Jose M Ferreira;
PUBLISHED: 1993, SOURCE: Atas do ENDIEL1993
INDEXED IN: Handle
60
TITLE: An HDL-based approach to BIST of 1149.1 - compatible boards
AUTHORS: José M Ferreira; Gustavo Alves; J. Ramalho; Manuel Gericota;
PUBLISHED: 1993
INDEXED IN: Handle
Page 6 of 7. Total results: 61.