Aleksandar Ilic
AuthID: R-001-NJ1
51
TITLE: GPGPU Power Modeling for Multi-Domain Voltage-Frequency Scaling
AUTHORS: Guerreiro, J; Ilic, A; Roma, N ; Tomas, P ;
PUBLISHED: 2018, SOURCE: 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) in 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), VOLUME: 2018-February
AUTHORS: Guerreiro, J; Ilic, A; Roma, N ; Tomas, P ;
PUBLISHED: 2018, SOURCE: 24th IEEE International Symposium on High Performance Computer Architecture (HPCA) in 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), VOLUME: 2018-February
52
TITLE: Path matrix and path energy of graphs PDF
AUTHORS: Aleksandar Ilic; Milan Basic;
PUBLISHED: 2018, SOURCE: CoRR, VOLUME: abs/1810.04870
AUTHORS: Aleksandar Ilic; Milan Basic;
PUBLISHED: 2018, SOURCE: CoRR, VOLUME: abs/1810.04870
INDEXED IN: 
DBLP 
arXiv
DBLP arXiv IN MY: DBLP
DBLP53
TITLE: Accelerating CNN computation: quantisation tuning and network resizing
AUTHORS: Alexandre Vieira; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2018, SOURCE: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
AUTHORS: Alexandre Vieira; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2018, SOURCE: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
INDEXED IN: DBLP
DBLP IN MY: DBLP
DBLP54
TITLE: Cache-Aware Roofline Model and Medical Image Processing Optimizations in GPUs
AUTHORS: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLISHED: 2018, SOURCE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
AUTHORS: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLISHED: 2018, SOURCE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
INDEXED IN: DBLP
DBLP IN MY: DBLP
DBLP56
TITLE: GPU Parallelization of HEVC In-Loop Filters
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: International Journal of Parallel Programming, VOLUME: 45, ISSUE: 6
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: International Journal of Parallel Programming, VOLUME: 45, ISSUE: 6
INDEXED IN: 
Scopus DBLP
Scopus DBLP IN MY: DBLP
DBLP57
TITLE: GHEVC: An Efficient HEVC Decoder for Graphics Processing Units Full Text
AUTHORS: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, ISSUE: 3
AUTHORS: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, ISSUE: 3
59
TITLE: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
60
TITLE: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
