Aleksandar Ilic
AuthID: R-001-NJ1
61
TITLE: GHEVC: An Efficient HEVC Decoder for Graphics Processing Units Full Text
AUTHORS: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, ISSUE: 3
AUTHORS: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, ISSUE: 3
63
TITLE: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
AUTHORS: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa; Miguel A Vega Rodríguez;
PUBLISHED: 2017, SOURCE: Concurrency and Computation: Practice and Experience, VOLUME: 29, ISSUE: 8
64
TITLE: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
AUTHORS: David Pereira; Aleksandar Ilic; Leonel Sousa;
PUBLISHED: 2017, SOURCE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
65
TITLE: Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
AUTHORS: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
AUTHORS: Andre Lopes; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
66
TITLE: Cache-aware Roofline Model in Intel® Advisor
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
INDEXED IN: 
DBLP
DBLP IN MY: DBLP
DBLP67
TITLE: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
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DBLP68
TITLE: Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model
AUTHORS: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
AUTHORS: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
DBLP IN MY: DBLP
DBLP69
TITLE: GPU Parallelization of HEVC In-Loop Filters
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, ISSUE: 6
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, ISSUE: 6
INDEXED IN: 
WOS 
CrossRef
WOS CrossRef70
TITLE: Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
AUTHORS: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLISHED: 2017, SOURCE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
AUTHORS: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLISHED: 2017, SOURCE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
INDEXED IN: DBLP
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DBLP