21
TITLE: Quaternary logic lookup table in standard CMOS
AUTHORS: Brito, D; Rabuske, TG; Fernandes, JR; Flores, P; Monteiro, J;
PUBLISHED: 2015, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus
22
TITLE: Efficient Design of FIR Filters Using Hybrid Multiple Constant Multiplications on FPGA
AUTHORS: Levent Aksoy; Paulo Flores; Jose Monteiro;
PUBLISHED: 2014, SOURCE: 32nd IEEE International Conference on Computer Design (ICCD) in 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
INDEXED IN: WOS
23
TITLE: Optimization of design complexity in time-multiplexed constant multiplications
AUTHORS: Levent Aksoy; Paulo Flores; Jose Monteiro;
PUBLISHED: 2014, SOURCE: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
INDEXED IN: CrossRef
IN MY: ORCID
24
TITLE: Exploration of tradeoffs in the design of integer cosine transforms for image compression
AUTHORS: Aksoy, L; Costa, E; Flores, P; Monteiro, J;
PUBLISHED: 2013, SOURCE: 2013 European Conference on Circuit Theory and Design, ECCTD 2013 in 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings
INDEXED IN: Scopus CrossRef: 1
IN MY: ORCID
25
TITLE: SIREN. a depth-first search algorithm for the filter design optimization problem
AUTHORS: Levent Aksoy; Paulo Flores; José Monteiro;
PUBLISHED: 2013, SOURCE: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13
INDEXED IN: CrossRef
IN MY: ORCID
26
TITLE: Combination of radix-2<sup>m</sup> multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Jose C Monteiro;
PUBLISHED: 2013, SOURCE: 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)
INDEXED IN: CrossRef: 3
IN MY: ORCID
27
TITLE: Design and Characterization of a QLUT in a Standard CMOS Process
AUTHORS: Diogo Brito; Jorge Fernandes; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: WOS
28
TITLE: Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition
AUTHORS: Sidinei Ghissoni; Eduardo Costa; Jose Monteiro; Ricardo Reis;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: WOS
29
TITLE: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs
AUTHORS: Levent Aksoy; Eduardo Costa; Paulo Flores; Jose Monteiro;
PUBLISHED: 2012, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)
INDEXED IN: WOS
30
TITLE: Power macro-modeling using an iterative LS-SVM method
AUTHORS: Gusmão, A; Silveira, L. Miguel ; Monteiro, J;
PUBLISHED: 2011, SOURCE: 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009 in IFIP Advances in Information and Communication Technology, VOLUME: 360
INDEXED IN: Scopus CrossRef
IN MY: ORCID
Page 3 of 6. Total results: 52.