José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
51
TITLE: Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
52
TITLE: Power estimation methods for sequential logic circuits Full Text
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
