A 10B 700 Ms/S Single-Channel 1B/Cycle Sar Adc Using a Monotonic-Specific Feedback Sar Logic With Power-Delay-Optimized Unbalanced N/P-Mos Sizing

AuthID
 P-00Z-DP0
6
Author(s)
Guo, MQ
·
Qi, L
·
Zhao, WB
·
Xiao, GJ
·
Sin, SW
Document Type
Article in Press
Year published
2023
Published
in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
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Publication Identifiers
Wos: WOS:001095733800001
Source Identifiers
ISSN: 1549-8328
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