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SEER: Probabilistic Scheduling for Hardware Transactional Memory
AuthID
P-015-9TE
3
Author(s)
Diegues N.
·
Romano P.
·
Garbatov S.
Document Type
Proceedings Paper
Year published
2015
Published
in
Annual ACM Symposium on Parallelism in Algorithms and Architectures
Volume: 2015-June, Pages: 224-233 (9)
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Publication Identifiers
DOI
:
10.1145/2755573.2755578
SCOPUS
: 2-s2.0-84946027466
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