An Efficient Performance-Driven Analog Ic Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance Regressors

AuthID
 P-018-3GP
2
Author(s)
Lourenco, N
Document Type
Proceedings Paper
Year published
2024
Published
in IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, ISSN: 2324-8432
Conference
32Nd Ifip/Ieee International Conference on Very Large Scale Integration, Vlsi-Soc 2024, Date: 6 October 2024 through 9 October 2024, Location: Tanger
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Publication Identifiers
Scopus: 2-s2.0-85217616215
Source Identifiers
ISSN: 2324-8432
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