Switched-Capacitor Decimators Combining Low-Sensitivity Ladder Structures with High-Speed Polyphase Networks

AuthID
 P-001-F8C
3
Author(s)
daFranca, JE
·
Document Type
Article
Year published
1996
Published
in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN: 1549-7747
Volume: 43, Issue: 1, Pages: 31-38 (8)
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Publication Identifiers
Scopus: 2-s2.0-0029778565
Wos: WOS:A1996TU60800004
Source Identifiers
ISSN: 1549-7747
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