An 8-Bit 0.35-V 5.04-Fj/Conversion-Step Sar Adc With Background Self-Calibration of Comparator Offset

AuthID
 P-00G-CD9
4
Author(s)
Document Type
Article
Year published
2015
Published
in IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ISSN: 1063-8210
Volume: 23, Issue: 7, Pages: 1301-1307 (7)
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Publication Identifiers
SCOPUS: 2-s2.0-84934274386
Wos: WOS:000356879200011
Source Identifiers
ISSN: 1063-8210
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