Sensitivity Aware Nsga-Ii Based Pareto Front Generation for the Optimal Sizing of Analog Circuits

AuthID
 P-00K-NYV
6
Author(s)
Garbaya, A
·
Kotti, M
·
Document Type
Article
Year published
2016
Published
in INTEGRATION-THE VLSI JOURNAL, ISSN: 0167-9260
Volume: 55, Pages: 220-226 (7)
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Publication Identifiers
SCOPUS: 2-s2.0-84978909882
Wos: WOS:000386401500020
Source Identifiers
ISSN: 0167-9260
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