An 8-Bit 0.35-V 5.04-Fj/Conversion-Step Sar Adc with Background Self-Calibration of Comparator Offset

AuthID
 P-00M-Y59
4
Author(s)
Rodrigues, C
Document Type
Article
Year published
2015
Published
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ISSN: 1063-8210
Volume: 23, Issue: 7, Pages: 1301-1307
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Publication Identifiers
Scopus: 2-s2.0-85027923752
Source Identifiers
ISSN: 1063-8210
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