Layout-Aware Sizing of Analog Ics Using Floorplan & Routing Estimates for Parasitic Extraction

AuthID
P-00N-88A
3
Author(s)
Document Type
Proceedings Paper
Year published
2015
Published
in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) in Design Automation and Test in Europe Conference and Exhibition, ISSN: 1530-1591
Volume: 2015-April, Pages: 1156-1161 (6)
Conference
Conference on Design Automation Test in Europe (Date), Date: MAR 09-13, 2015, Location: Alpexpo Congress Center, Grenoble, FRANCE, Sponsors: European Design & Automation Association, Elect Design Automation Consortium, IEEE Council on Elec Design Automation, European Elect Chips & Syst design Initiative, ACM Special Interest Grp on Design Automation, Russian Acad of Sciences, IEEE Comp Soc test technology tech Council (tttC), IEEE Solid-State Circuits Soc (SSCS), International Federation for Information Processing (IFIP), Ville De Grenoble, LETI, ST, MINALOGIC, Agence DEtudes et de Promotion de lIsere, Rhone Alpes, Grenoble Alpes, CMP, Systematic Paris Region Systems & ICT, Cluster SCC, JEITA, Synopsys, Mentor Graphics, Cadence, MathWorks, EUROTRAINING, Host: Alpexpo Congress Center
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Publication Identifiers
SCOPUS: 2-s2.0-84940843255
Wos: WOS:000380393200214
Source Identifiers
ISSN: 1530-1591
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