High-Level Algorithms for the Optimization of Gate-Level Area in Digit-Serial Multiple Constant Multiplications

AuthID
 P-002-9GT
5
Author(s)
Document Type
Article
Year published
2012
Published
in INTEGRATION-THE VLSI JOURNAL, ISSN: 0167-9260
Volume: 45, Issue: 3, Pages: 294-306 (13)
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Publication Identifiers
Scopus: 2-s2.0-84860516076
Wos: WOS:000304792100008
Source Identifiers
ISSN: 0167-9260
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