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Power-Efficient Approximate Sad Architecture with Loa Imprecise Adders

AuthID
P-00Q-FAV

Author(s)

Porto, R

Agostini, L

Zatt, B

Roma, N

Porto, M

Document Type

Proceedings Paper

Year published

2019

Published

in 2019 IEEE 10th Latin American Symposium on Circuits and Systems, LASCAS 2019 - Proceedings

Pages: 65-68

Conference

10Th Ieee Latin American Symposium on Circuits and Systems, Lascas 2019, Date: 24 February 2019 through 27 February 2019, Sponsors: IEEE;IEEE Circuits and Systems Society (CAS);IEEE Council on Electronic Design Automation (CEDA)

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Publication Identifiers

DOI: 10.1109/lascas.2019.8667554

SCOPUS: 2-s2.0-85064153776

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Power-Efficient Approximate Sad Architecture with Loa Imprecise Adders

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