Toggle navigation
Publications
Researchers
Institutions
0
Sign In
Federated Authentication
(Click on the image)
Local Sign In
Password Recovery
Register
Sign In
Publications
Search
Statistics
Stretching the Capacity of Hardware Transactional Memory in Ibm Power Architectures
AuthID
P-00Q-FCK
4
Author(s)
Filipe, R
·
Issa, S
·
Romano, P
·
Barreto, J
Document Type
Proceedings Paper
Year published
2019
Published
in
PROCEEDINGS OF THE 24TH SYMPOSIUM ON PRINCIPLES AND PRACTICE OF PARALLEL PROGRAMMING (PPOPP '19)
Pages: 107-119 (13)
Conference
24Th Acm Sigplan Symposium on Principles and Practice of Parallel Programming (Ppopp),
Date:
FEB 16-20, 2019,
Location:
Washington, DC,
Sponsors:
Assoc Comp Machinery, ACM SIGPLAN, ACM SIGHPC
Indexing
Wos
®
Scopus
®
Crossref
®
3
Google Scholar
®
Metadata
Sources
Publication Identifiers
DOI
:
10.1145/3293883.3295714
SCOPUS
: 2-s2.0-85064231525
Wos
: WOS:000587604600010
Export Publication Metadata
Export
×
Publication Export Settings
BibTex
EndNote
APA
Export Preview
Marked List
Add to Marked List
Info
At this moment we don't have any links to full text documens.
×
Select Source
This publication has:
2 records from
ISI
2 records from
SCOPUS
2 records from
DBLP
2 records from
Unpaywall
2 records from
Openlibrary
2 records from
Handle
Please select which records must be used by Authenticus!
×
Preview Publications
© 2024 CRACS & Inesc TEC - All Rights Reserved
Privacy Policy
|
Terms of Service