Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency Ics

AuthID
 P-00V-DN3
8
Author(s)
Canelas, A
·
Passos, F
·
Roca, E
·
Castro Lopez, R
·
Fernandez, FV
Document Type
Article
Year published
2021
Published
in IEEE ACCESS, ISSN: 2169-3536
Volume: 9, Pages: 124152-124164 (13)
Indexing
Wos®
Scopus®
Crossref®4
Google Scholar®
Publication Identifiers
Scopus: 2-s2.0-85114744685
Wos: WOS:000696059300001
Source Identifiers
ISSN: 2169-3536
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