Configurable M-Factor Vlsi Dvb-S2 Ldpc Decoder Architecture with Optimized Memory Tiling Design

AuthID
 P-002-G6A
5
Author(s)
Cacheira, J
Document Type
Article
Year published
2012
Published
in EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING, ISSN: 1687-1499
Volume: 2012, Issue: 1, Pages: 98 (16)
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Wos®
Scopus®
Dblp®/en/publications/view/82122
Crossref®4
Google Scholar®
Publication Identifiers
DBLP: journals/ejwcn/FernandesGSSC12
SCOPUS: 2-s2.0-84872838646
Wos: WOS:000305958800001
Source Identifiers
ISSN: 1687-1499
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