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Power-And-Area Efficient 14-Bit 1.5 Msample/S Two-Stage Algorithmic Adc Based on a Mismatch-Insensitive Mdac

AuthID
P-004-4G2

Author(s)

Esperanca, B

Goes, J

Tavares, R

Galhardo, A

Paulino, N

Silva, MM

Document Type

Proceedings Paper

Year published

2008

Published

in PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 in IEEE International Symposium on Circuits and Systems, ISSN: 0271-4302

Pages: 220-223 (4)

Conference

Ieee International Symposium on Circuits and Systems, Date: MAY 18-21, 2008, Location: Seattle, WA, Sponsors: IEEE

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Publication Identifiers

DOI: 10.1109/iscas.2008.4541394

Scopus: 2-s2.0-51749094634

Wos: WOS:000258532100057

Source Identifiers

ISSN: 0271-4302

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Power-And-Area Efficient 14-Bit 1.5 Msample/S Two-Stage Algorithmic Adc Based on a Mismatch-Insensitive Mdac

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Power-And-Area Efficient 14-Bit 1.5 Msample/S Two-Stage Algorithmic Adc Based on a Mismatch-Insensitive Mdac

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