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Reducing Misses to External Memory Accesses in Task-Level Pipelining
AuthID
P-00G-SYF
2
Author(s)
Azarian, A
·
Cardoso, JMP
Document Type
Proceedings Paper
Year published
2015
Published
in
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
in
IEEE International Symposium on Circuits and Systems,
ISSN: 0271-4302
Volume: 2015-July, Pages: 1422-1425 (4)
Conference
Ieee International Symposium on Circuits and Systems (Iscas),
Date:
MAY 24-27, 2015,
Location:
Lisbon, PORTUGAL,
Sponsors:
IEEE
Indexing
Wos
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Scopus
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Dblp
®
/en/publications/view/550863
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Metadata
Sources
Publication Identifiers
DOI
:
10.1109/iscas.2015.7168910
DBLP
: conf/iscas/AzarianC15
SCOPUS
: 2-s2.0-84946222134
Wos
: WOS:000371471001176
Source Identifiers
ISSN
: 0271-4302
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