AIDA: Layout-Aware Analog Circuit-Level Sizing with In-Loop Layout Generation

AuthID
 P-00M-64T
5
Author(s)
Document Type
Article
Year published
2016
Published
in INTEGRATION-THE VLSI JOURNAL, ISSN: 0167-9260
Volume: 55, Pages: 316-329 (14)
Indexing
Wos®
Scopus®
Crossref®16
Google Scholar®
Publication Identifiers
SCOPUS: 2-s2.0-84966648845
Wos: WOS:000386401500031
Source Identifiers
ISSN: 0167-9260
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