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Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
AuthID
P-00M-AM7
3
Author(s)
Paulino, NMC
·
Ferreira, JC
·
Cardoso, JMP
Document Type
Article
Year published
2017
Published
in
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
ISSN: 1063-8210
Volume: 25, Issue: 1, Pages: 21-34 (14)
Indexing
Wos
®
Scopus
®
Dblp
®
/en/publications/view/666247
Crossref
®
6
Google Scholar
®
Metadata
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Publication Identifiers
DOI
:
10.1109/tvlsi.2016.2573640
DBLP
: journals/tvlsi/PaulinoFC17
SCOPUS
: 2-s2.0-84979067006
Wos
: WOS:000394591600002
Source Identifiers
ISSN
: 1063-8210
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