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Seven-Bit 700-Ms/S Four-Way Time-Interleaved Sar Adc With Partial V-Cm-Based Switching
AuthID
P-00M-GZG
8
Author(s)
Xing, DZ
·
Zhu, Y
·
Chan, CH
·
Sin, SW
·
Ye, F
·
Ren, JY
·
U, SP
·
Martins, RP
Document Type
Article
Year published
2017
Published
in
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
ISSN: 1063-8210
Volume: 25, Issue: 3, Pages: 1168-1172 (5)
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®
Scopus
®
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®
Metadata
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Publication Identifiers
DOI
:
10.1109/tvlsi.2016.2610864
Scopus
: 2-s2.0-85014077920
Wos
: WOS:000395894000034
Source Identifiers
ISSN
: 1063-8210
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