Fast Iterative Circuits and Ram-Based Mergers to Accelerate Data Sort in Software/Hardware Systems [Kiired Iteratiivsed Ahelad Ja Ram-I Baasil Ühendajad, Kiirendamaks Andmete Sortimist Riist- Ning Tarkvara Süsteemides]

AuthID
 P-00M-Y0J
4
Author(s)
Document Type
Article
Year published
2017
Published
in Proceedings of the Estonian Academy of Sciences, ISSN: 1736-6046
Volume: 66, Issue: 3, Pages: 323-335
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SCOPUS: 2-s2.0-85028310572
Source Identifiers
ISSN: 1736-6046
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