A 3Rd Order Mash Switched-Capacitor Sigma Delta M Using Ultra Incomplete Settling Employing an Area Reduction Technique

AuthID
 P-00N-P03
2
Author(s)
Fouto, D
·
Document Type
Proceedings Paper
Year published
2017
Published
in 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) in IEEE International Symposium on Circuits and Systems, ISSN: 0271-4302
Pages: 551-554 (4)
Conference
Ieee International Symposium on Circuits and Systems (Iscas), Date: MAY 28-31, 2017, Location: Baltimore, MD, Sponsors: IEEE, IEEE Circuits & Syst Soc
Indexing
Wos®
Publication Identifiers
Wos: WOS:000424890100133
Source Identifiers
ISSN: 0271-4302
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