Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage Otas by Using Differential Voltage Combiners

AuthID
 P-00P-9HW
5
Author(s)
Borrego, R
·
Oliveira, J
·
Goes, J
1
Editor(s)
Napieralski, A
Document Type
Proceedings Paper
Year published
2013
Published
in MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, MIXDES 2013
Pages: 247-250 (4)
Conference
20Th International Conference on Mixed Design of Integrated Circuits and Systems (Mixdes 2013), Date: JUN 20-22, 2013, Location: Gdynia, POLAND, Sponsors: Lodz Univ Technol, Dept Microelectron & Comp Sci, Gdynia Maritime Univ, Inst Microelectron & Optoelectron, DMCS, IEEE, ELECTRON DEVICES SOC, PAN, URSI
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Wos: WOS:000399863600042
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