Planar Dual-Gate Paper/Oxide Field Effect Transistors as Universal Logic Gates

AuthID
 P-00P-TJH
6
Author(s)
Gaspar, D
·
Martins, J
·
Bahubalindruni, P
·
Martins, R
Document Type
Article
Year published
2018
Published
in ADVANCED ELECTRONIC MATERIALS, ISSN: 2199-160X
Volume: 4, Issue: 12
Indexing
Wos®
Scopus®
Crossref®24
Google Scholar®
Publication Identifiers
Scopus: 2-s2.0-85055740789
Wos: WOS:000452617800010
Source Identifiers
ISSN: 2199-160X
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