Toggle navigation
Publications
Researchers
Institutions
0
Sign In
Federated Authentication
(Click on the image)
Local Sign In
Password Recovery
Register
Sign In
Publications
Search
Statistics
Time-Predictable Task-To-Thread Mapping in Multi-Core Processors
AuthID
P-010-0TW
5
Author(s)
Samadi, M
·
Royuela, S
·
Pinho, LM
·
Carvalho, T
·
Quinones, E
Document Type
Article
Year published
2024
Published
in
JOURNAL OF SYSTEMS ARCHITECTURE,
ISSN: 1383-7621
Volume: 148, Pages: 103068 (18)
Indexing
Wos
®
Scopus
®
Crossref
®
Google Scholar
®
Metadata
Sources
Publication Identifiers
DOI
:
10.1016/j.sysarc.2024.103068
SCOPUS
: 2-s2.0-85185008119
Wos
: WOS:001188910500001
Source Identifiers
ISSN
: 1383-7621
Export Publication Metadata
Export
×
Publication Export Settings
BibTex
EndNote
APA
Export Preview
Marked List
Add to Marked List
Info
At this moment we don't have any links to full text documens.
×
Select Source
This publication has:
2 records from
ISI
2 records from
SCOPUS
2 records from
DBLP
2 records from
Unpaywall
2 records from
Openlibrary
2 records from
Handle
Please select which records must be used by Authenticus!
×
Preview Publications
© 2024 CRACS & Inesc TEC - All Rights Reserved
Privacy Policy
|
Terms of Service