Luís Jorge Brás Monteiro Guerra e Silva


AuthID: R-000-9HS

Confirmed Publications: 12



1
TITLE: Improving SAT solver efficiency using a multi-core approach
AUTHORS: Marques, R; Guerra E Silva, L ; Flores, P; Silveira, L. Miguel ;
PUBLISHED: 2013, SOURCE: 26th International Florida Artificial Intelligence Research Society Conference, FLAIRS 2013 in FLAIRS 2013 - Proceedings of the 26th International Florida Artificial Intelligence Research Society Conference
INDEXED IN: Scopus
IN MY: ORCID
2
TITLE: TAU 2013 variation aware timing analysis contest
AUTHORS: Sinha, D; Guerra E Silva, L ; Wang, J; Raghunathan, S; Netrabile, D; Shebaita, A;
PUBLISHED: 2013, SOURCE: 2013 ACM International Symposium on Physical Design, ISPD 2013 in Proceedings of the International Symposium on Physical Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
3
TITLE: Unifying functional and parametric timing verification
AUTHORS: De Silva, LG ;
PUBLISHED: 2012, SOURCE: 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
INDEXED IN: Scopus CrossRef
IN MY: ORCID
4
TITLE: Handling intra-die variations in PSTA
AUTHORS: Guerra E Silva, L ; Silveira, L. Miguel ;
PUBLISHED: 2011, SOURCE: 21st Great Lakes Symposium on VLSI, GLSVLSI 2011 in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
INDEXED IN: Scopus CrossRef
IN MY: ORCID
5
TITLE: Effective Corner-Based Techniques for Variation-Aware IC Timing Verification  Full Text
AUTHORS: Luis G E Guerra e Silva ; Joel Phillips; Silveira, L. Miguel ;
PUBLISHED: 2010, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 29, ISSUE: 1
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
6
TITLE: Speedpath analysis under parametric timing models  Full Text
AUTHORS: E Silva, LG ; Phillips, JR; Silveira, L. Miguel ;
PUBLISHED: 2010, SOURCE: 47th Design Automation Conference, DAC '10 in Proceedings - Design Automation Conference
INDEXED IN: Scopus CrossRef
IN MY: ORCID
7
TITLE: Library compatible variational delay computation  Full Text
AUTHORS: Luis G E Guerra e Silva ; Zhenhai H Zhu; Joel R Phillips; Silveira, L. Miguel ;
PUBLISHED: 2008, SOURCE: 14th International Conference on Very Large Scale Integration of System on Chip in VLSI-SOC: RESEARCH TRENDS IN VLSI AND SYSTEMS ON CHIP, VOLUME: 249
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
8
TITLE: Efficient computation of the worst-delay corner  Full Text
AUTHORS: Luis Guerra E Silva ; Silveira, L. Miguel ; Joel R Phillips;
PUBLISHED: 2007, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE 07) in 2007 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
9
TITLE: Variation-aware, library compatible delay modeling strategy
AUTHORS: Luis Guerra E Silva ; Zhenhai H Zhu; Joel R Phillips; Silveira, L. Miguel ;
PUBLISHED: 2006, SOURCE: International Conference on Very Large Scale Integration and System-on-Chip in IFIP VLSI-SoC 2006: IFIP WG 10.5 International Conference on Very Large Scale Integration & System-on-Chip
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
10
TITLE: Solving satisfiability in combinational circuits  Full Text
AUTHORS: Marques Silva, J ; Silva, LGE ;
PUBLISHED: 2003, SOURCE: IEEE DESIGN & TEST OF COMPUTERS, VOLUME: 20, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 10 Unpaywall
IN MY: ORCID
Page 1 of 2. Total results: 12.

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