Nuno Cavaco Gomes Horta


AuthID: R-000-DMG

Confirmed Publications: 270



91
TITLE: New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
AUTHORS: Lourenco, N ; Martins, R; Povoa, R; Canelas, A; Horta, N ; Passos, F; Castro Lopez, R; Roca, E; Fernandez, FV;
PUBLISHED: 2017, SOURCE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
92
TITLE: Related Work
AUTHORS: João Leitão; Rui Ferreira Neves; Nuno C G Horta ;
PUBLISHED: 2017, SOURCE: Identifying Patterns in Financial Markets - SpringerBriefs in Applied Sciences and Technology
INDEXED IN: CrossRef
IN MY: ORCID
93
TITLE: Stochastic-based placement template generator for analog IC layout-aware synthesis
AUTHORS: Martins, R; Lourenço, N ; Canelas, A; Horta, N ;
PUBLISHED: 2017, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 58
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
94
TITLE: Systematic design of a voltage controlled oscillator using a layout-aware approach
AUTHORS: Passos, F; Roca, E; Castro Lopez, R; Fernandez, FV; Martins, R; Lourenco, N ; Povoa, R; Canelas, A; Horta, N ;
PUBLISHED: 2017, SOURCE: 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017 in SMACD 2017 - 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
INDEXED IN: Scopus CrossRef
IN MY: ORCID
95
TITLE: Using Sentiment from Twitter optimized by Genetic Algorithms to Predict the Stock Marke
AUTHORS: Simoes, C; Neves, R; Horta, N ;
PUBLISHED: 2017, SOURCE: IEEE Congress on Evolutionary Computation (CEC) in 2017 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC)
INDEXED IN: Scopus WOS CrossRef: 2
IN MY: ORCID
96
TITLE: AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation  Full Text
AUTHORS: Nuno Lourenco ; Ricardo Martins ; Antonio Canelas; Ricardo Povoa; Nuno Horta ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS CrossRef: 16
IN MY: ORCID
97
TITLE: An 8bit Logarithmic AD Converter Using Cross-Coupled Inverters and a Time-to-Digital Converter
AUTHORS: Santos, M; Horta, N ; Guilherme, J;
PUBLISHED: 2016, SOURCE: 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) in 2016 12TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
98
TITLE: Analog integrated circuit design automation: Placement, routing and parasitic extraction techniques
AUTHORS: Martins, R; Lourenço, N; Horta, N ;
PUBLISHED: 2016, SOURCE: Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques
INDEXED IN: Scopus CrossRef
IN MY: ORCID
99
TITLE: Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach
AUTHORS: Andre Ferreira; Nuno Lourenco ; Ricardo Martins; Nuno Horta ;
PUBLISHED: 2016, SOURCE: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2016 13TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
100
TITLE: Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
AUTHORS: Lourenço, N ; Martins, R; Horta, N ;
PUBLISHED: 2016, SOURCE: Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
INDEXED IN: Scopus CrossRef
IN MY: ORCID
Page 10 of 27. Total results: 270.

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