Gustavo Ribeiro da Costa Alves


AuthID: R-000-K2T

Confirmed Publications: 253



241
TITLE: Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test
AUTHORS: Manuel G Gericota; Gustavo R. Alves ; José M Ferreira;
PUBLISHED: 2001, SOURCE: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001.
INDEXED IN: DBLP Handle
IN MY: DBLP
242
TITLE: Implementing a Self-Checking PROFIBUS Slave
AUTHORS: Margrit Reni Krug; Marcelo Lubaszewski; José Manuel Martins Ferreira; Gustavo R. Alves ;
PUBLISHED: 2000, SOURCE: 1st Latin American Test Workshop, LATW 2000, Rio de Janeiro, RJ, Brazil, March 13-15, 2000.
INDEXED IN: DBLP
IN MY: DBLP
243
TITLE: A system verification strategy based on the BST infrastructure
AUTHORS: Gustavo R. Alves ; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99) in ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI
INDEXED IN: WOS DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
244
TITLE: Board-level prototype validation: A built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Amaral, T; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99) in ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI
INDEXED IN: WOS
IN MY: ORCID | CIÊNCIAVITAE
245
TITLE: Board-level prototype validation: a built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Telmo Amaral; Martins Ferreira Jose, M;
PUBLISHED: 1999, SOURCE: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
INDEXED IN: Scopus
IN MY: ORCID
246
TITLE: Board-level prototype validation: a built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Tito G B Amaral; José M M Ferreira;
PUBLISHED: 1999, SOURCE: International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA
INDEXED IN: DBLP CrossRef: 2
IN MY: ORCID | DBLP | CIÊNCIAVITAE
247
TITLE: From design-for-test to design-for-debug-and-test: Analysis of requirements and limitations for 1149.1  Full Text
AUTHORS: Gustavo R. Alves ; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 17th IEEE Very Large Scale Intergration Test Symposium in 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 5
IN MY: ORCID | DBLP | CIÊNCIAVITAE
248
249
TITLE: System verification strategy based on the BST infrastructure
AUTHORS: Gustavo R. Alves ; Martins Ferreira Jose, M;
PUBLISHED: 1999, SOURCE: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
250
TITLE: Using the BS register for capturing and storing n-bit sequences in real-time
AUTHORS: Gustavo R. Alves ; José Manuel Martins Ferreira;
PUBLISHED: 1999, SOURCE: 1999 European Test Workshop, ETW 1999 in 4th European Test Workshop, ETW 1999, Constance, Germany, May 25-28, 1999
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
Page 25 of 26. Total results: 253.

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