Hector Pettenghi Roldan


AuthID: R-000-XX8

Confirmed Publications: 8



1
TITLE: DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
AUTHORS: Ambrose, JA; Pettenghi, H ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXED IN: Scopus DBLP CrossRef
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2
TITLE: Method to Design General RNS Reverse Converters for Extended Moduli Sets
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 60, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef
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3
TITLE: Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks
AUTHORS: Jude Angelo Ambrose; Hector Pettenghi ; Darshana Jayasinghe; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IET CIRCUITS DEVICES & SYSTEMS, VOLUME: 7, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef
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4
TITLE: RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 60, ISSUE: 6
INDEXED IN: Scopus WOS DBLP CrossRef
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5
TITLE: Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion
AUTHORS: Hector Pettenghi ; Leonel Sousa ; Jude Angelo Ambrose;
PUBLISHED: 2012, SOURCE: 17th Asia and South Pacific Design Automation Conference (ASP-DAC) in 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
INDEXED IN: Scopus WOS DBLP CrossRef
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6
TITLE: RNS arithmetic units for modulo {2n±k}
AUTHORS: Matutino, PM; Pettenghi, H ; Chaves, R ; Sousa, L ;
PUBLISHED: 2012, SOURCE: 15th Euromicro Conference on Digital System Design, DSD 2012 in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
INDEXED IN: Scopus DBLP CrossRef
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7
TITLE: Improved Nanopipelined RTD Adder Using Generalized Threshold Gates
AUTHORS: Hector Pettenghi ; Maria J Avedillo; Jose M Quintana;
PUBLISHED: 2011, SOURCE: IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOLUME: 10, ISSUE: 1
INDEXED IN: Scopus WOS CrossRef
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8
TITLE: An improved RNS generator 2(n) +/- k based on threshold logic
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ; Maria J Avedillo;
PUBLISHED: 2010, SOURCE: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip in PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID

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