Nuno Calado Correia Lourenço


AuthID: R-001-GD2

Confirmed Publications: 79



11
TITLE: Automated Analog IC Design Constraints Generation for a Layout-Aware Sizing Approach
AUTHORS: Andre Ferreira; Nuno Lourenco ; Ricardo Martins; Nuno Horta ;
PUBLISHED: 2016, SOURCE: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2016 13TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXED IN: Scopus WOS CrossRef
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12
TITLE: Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
AUTHORS: Lourenço, N ; Martins, R; Horta, N ;
PUBLISHED: 2016, SOURCE: Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
INDEXED IN: Scopus CrossRef
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13
TITLE: Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques  Full Text
AUTHORS: Povoa, R; Bastos, I; Lourenco, N ; Horta, N ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 52
INDEXED IN: Scopus WOS CrossRef
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14
TITLE: Current-flow and current-density-aware multi-objective optimization of analog IC placement  Full Text
AUTHORS: Ricardo Martins ; Ricardo Povoa; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS CrossRef
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15
TITLE: Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer  Full Text
AUTHORS: Mrinalinee Pandey; Antonio Canelas; Ricardo Povoa; Jorge Alves Torres; Costa Freire, JC; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2016, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 55
INDEXED IN: Scopus WOS CrossRef: 1
IN MY: ORCID
16
TITLE: Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach  Full Text
AUTHORS: David Neves; Ricardo Martins ; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2016, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
INDEXED IN: Scopus WOS
IN MY: ORCID
17
TITLE: On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies
AUTHORS: Ricardo Martins; Antonio Canelas; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2016, SOURCE: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2016 13TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
18
TITLE: Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations
AUTHORS: Antonio Canelas; Ricardo Martins; Ricardo Povoa; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2016, SOURCE: 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2016 13TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXED IN: Scopus WOS CrossRef: 2
IN MY: ORCID
19
TITLE: A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving
AUTHORS: Povoa, R; Lourenco, N ; Horta, N ; Goes, J;
PUBLISHED: 2015, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLUME: 2015-July
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
20
TITLE: AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing
AUTHORS: Bruno Cardoso; Ricardo Martins ; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2015, SOURCE: 2015 11th Conference on PhD Res in Microelect & Elect PRIME in 2015 11TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME)
INDEXED IN: Scopus WOS CrossRef
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Page 2 of 8. Total results: 79.

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