Nuno Calado Correia Lourenço


AuthID: R-001-GD2

Confirmed Publications: 79



31
TITLE: Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction
AUTHORS: Lourenco, N ; Martins, R ; Horta, N ;
PUBLISHED: 2015, SOURCE: Conference on Design Automation Test in Europe (DATE) in 2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), VOLUME: 2015-April
INDEXED IN: Scopus WOS
IN MY: ORCID
32
TITLE: Multi-objective framework implementation
AUTHORS: Lourenço, R; Lourenço, N ; Horta, N ;
PUBLISHED: 2015, SOURCE: SpringerBriefs in Applied Sciences and Technology, ISSUE: 9783319159546
INDEXED IN: Scopus CrossRef
IN MY: ORCID
33
TITLE: Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates  Full Text
AUTHORS: Ricardo Martins ; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2015, SOURCE: EXPERT SYSTEMS WITH APPLICATIONS, VOLUME: 42, ISSUE: 23
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
34
TITLE: Preface
AUTHORS: Lourenço, R; Lourenço, N ; Horta, N;
PUBLISHED: 2015, SOURCE: SpringerBriefs in Applied Sciences and Technology, ISSUE: 9783319159546
INDEXED IN: Scopus
IN MY: ORCID
35
TITLE: Previous works on automated analog IC sizing
AUTHORS: Lourenço, R; Lourenço, N ; Horta, N ;
PUBLISHED: 2015, SOURCE: SpringerBriefs in Applied Sciences and Technology, ISSUE: 9783319159546
INDEXED IN: Scopus CrossRef
IN MY: ORCID
36
TITLE: Results for analog IC design
AUTHORS: Lourenço, R; Lourenço, N ; Horta, N ;
PUBLISHED: 2015, SOURCE: SpringerBriefs in Applied Sciences and Technology, ISSUE: 9783319159546
INDEXED IN: Scopus CrossRef
IN MY: ORCID
37
TITLE: Scheduling Evaluation Tasks for Increased Efficiency of Parallel Analog IC Synthesis
AUTHORS: David Neves; Nuno Lourenco ; Nuno Horta ;
PUBLISHED: 2015, SOURCE: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) in 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
38
TITLE: A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner
AUTHORS: Povoa, R; Lourenco, N ; Horta, N ; Santos Tavares, R; Goes, J;
PUBLISHED: 2014, SOURCE: 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) in 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
39
TITLE: Electromigration-aware analog Router with multilayer multiport terminal structures  Full Text
AUTHORS: Ricardo Martins ; Nuno Lourenco ; Antonio Canelas; Nuno Horta ;
PUBLISHED: 2014, SOURCE: INTEGRATION-THE VLSI JOURNAL, VOLUME: 47, ISSUE: 4
INDEXED IN: Scopus WOS CrossRef: 16
IN MY: ORCID
40
TITLE: Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures  Full Text
AUTHORS: Ricardo Martins ; Nuno Lourenco ; Antonio Canelas; Nuno Horta ;
PUBLISHED: 2014, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in 2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE)
INDEXED IN: Scopus WOS CrossRef: 2
IN MY: ORCID
Page 4 of 8. Total results: 79.

A place for researchers and their institutions

Useful Links

Get Help

© 2024 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service