91
TITLE: Message from general and program co-chairs
AUTHORS: Silvano, C; Cardoso, JMP ; Agosta, G; Huebner, M;
PUBLISHED: 2016, SOURCE: 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2016 in ACM International Conference Proceeding Series, VOLUME: Part F18-January-2016
INDEXED IN: Scopus
IN MY: ORCID
92
93
TITLE: Pipelining data-dependent tasks in FPGA-based multicore architectures  Full Text
AUTHORS: Ali Azarian ; Joao M P Cardoso ;
PUBLISHED: 2016, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 42
INDEXED IN: Scopus WOS DBLP CrossRef
95
TITLE: SSA-based MATLAB-to-C compilation and optimization
AUTHORS: Luís Reis ; João Bispo ; João M P Cardoso ;
PUBLISHED: 2016, SOURCE: 3rd ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming, ARRAY 2016 in Proceedings of the 3rd ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming, ARRAY@PLDI 2016, Santa Barbara, CA, USA, June 14, 2016
INDEXED IN: Scopus DBLP CrossRef: 4
96
TITLE: The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
AUTHORS: Cristina Silvano; Giovanni Agosta; Stefano Cherubin; Davide Gadioli; Gianluca Palermo; Andrea Bartolini; Luca Benini; Jan Martinovic; Martin Palkovic; Katerina Slaninová; João Bispo ; João M P Cardoso ; Rui Abreu ; Pedro Pinto ; Carlo Cavazzoni; Nico Sanna; Andrea R Beccari; Radim Cmar; Erven Rohou;
PUBLISHED: 2016, SOURCE: ACM International Conference on Computing Frontiers, CF 2016 in Proceedings of the ACM International Conference on Computing Frontiers, CF'16, Como, Italy, May 16-19, 2016
INDEXED IN: Scopus DBLP CrossRef: 21
97
TITLE: Towards a Multi-softcore FPGA Approach for the HOG Algorithm
AUTHORS: Jose Arnaldo M Mascagni de Holanda; Joao Manuel P Paiva Cardoso ; Eduardo Marques;
PUBLISHED: 2016, SOURCE: 14th IEEE International Conference on Industrial Informatics (INDIN) in 2016 IEEE 14TH INTERNATIONAL CONFERENCE ON INDUSTRIAL INFORMATICS (INDIN)
INDEXED IN: Scopus WOS DBLP CrossRef: 3
100
TITLE: A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2015, SOURCE: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, VOLUME: 7, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 3
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