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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
AuthID
P-00A-4B4
3
Author(s)
Paulino, N
·
Ferreira, JC
·
Cardoso, JMP
Document Type
Article
Year published
2015
Published
in
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS,
ISSN: 1936-7406
Volume: 7, Issue: 4, Pages: 29:1-29:20 (20)
Indexing
Wos
®
Scopus
®
Dblp
®
/en/publications/view/332132
Crossref
®
3
Google Scholar
®
Metadata
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Publication Identifiers
DOI
:
10.1145/2629468
DBLP
: journals/trets/PaulinoFC15
SCOPUS
: 2-s2.0-84911387509
Wos
: WOS:000350529900002
Source Identifiers
ISSN
: 1936-7406
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