João Paulo Cacho Teixeira


AuthID: R-000-7A4

Confirmed Publications: 110



101
TITLE: Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part I  Full Text
AUTHORS: Bafleur, M; Buxo, J; Teixeira, JP ; Teixeira, IC ;
PUBLISHED: 1992, SOURCE: Microelectronics Journal, VOLUME: 23, ISSUE: 8
INDEXED IN: Scopus
IN MY: ORCID
102
TITLE: Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part II  Full Text
AUTHORS: Teixeira, JP ; Teixeira, IC ; Bafleur, M; Buxo, J;
PUBLISHED: 1992, SOURCE: Microelectronics Journal, VOLUME: 23, ISSUE: 8
INDEXED IN: Scopus
IN MY: ORCID
103
TITLE: A methodology for testability enhancement at layout level
AUTHORS: Teixeira, JP ; Teixeira, IC ; Almeida, CFB; Goncalves, FM ; Goncalves, J;
PUBLISHED: 1991, SOURCE: Journal of Electronic Testing, VOLUME: 1, ISSUE: 4
INDEXED IN: Scopus CrossRef
IN MY: ORCID
104
TITLE: PHYSICAL DESIGN OF TESTABLE CMOS DIGITAL INTEGRATED-CIRCUITS
AUTHORS: DESOUSA, JJHT; GONCALVES, FM ; TEIXEIRA, JP ;
PUBLISHED: 1991, SOURCE: European Solid-State Circuits Conference 1990 - ESSCIRC '90 in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOLUME: 26, ISSUE: 7
INDEXED IN: Scopus WOS
105
TITLE: Bottom-up methodology for test preparation and refinement
AUTHORS: Gracio, JA; Bicudo, PA; Rua, NN; Oliveira, AM ; Almeida, CFB; Teixeira, JP ;
PUBLISHED: 1989, SOURCE: IEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 2
INDEXED IN: Scopus
IN MY: ORCID
106
TITLE: Logical timing simulator for CMOS circuits based on an accurate formulation of the propagation delay
AUTHORS: Bafleur, M; Buxo, J; Teixeira, JP ; Teixeira, IC ;
PUBLISHED: 1989, SOURCE: European Conference on Circuit Theory and Design in IEE Conference Publication, ISSUE: 308
INDEXED IN: Scopus
IN MY: ORCID
107
TITLE: Propagation delay modelling of MOS digital networks
AUTHORS: Costa Andre, J; Teixeira, JP ; Teixeira, IC ; Buxo, J; Bafleur, M;
PUBLISHED: 1989, SOURCE: Mediterranean Electrotechnical Conference (MELECON'89) - Proceedings
INDEXED IN: Scopus
IN MY: ORCID
108
TITLE: Test preparation and fault analysis using a bottom-up methodology
AUTHORS: Gracio, JA; Bicudo, PA; Rua, NN; Oliveira, AM ; Almeida, CFB; Teixeira, JP ;
PUBLISHED: 1989, SOURCE: Proceedings of the 1st European Test Conference
INDEXED IN: Scopus
IN MY: ORCID
109
TITLE: Bottom-up testing methodology for VLSI.
AUTHORS: Teixeira, JP ; Almeida, CFB; Gracio, JA; Bicudo, PA; Oliveira, AL; Rua, N;
PUBLISHED: 1988, SOURCE: Proceedings of the IEEE 1988 Custom Integrated Circuits Conference. in Proceedings of the Custom Integrated Circuits Conference
INDEXED IN: Scopus
IN MY: ORCID
110
TITLE: CIRCUIT SIMULATION OF MOS DIGITAL CIRCUITS.
AUTHORS: Pederneira, LF; Teixeira, JPC ;
PUBLISHED: 1987, SOURCE: Proceedings of MELECON '87: Mediterranean Electrotechnical Conference/34th Congress on Electronics Joint Conference.
INDEXED IN: Scopus
IN MY: ORCID
Page 11 of 11. Total results: 110.

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