Leonel Augusto Pires Seabra Sousa


AuthID: R-000-93B

Confirmed Publications: 283



61
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations  Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus CrossRef: 15
IN MY: ORCID
62
TITLE: SchedMon: A Performance and Energy Monitoring Tool for Modern Multi-cores
AUTHORS: Luis Tanica; Aleksandar Ilic; Pedro Tomas ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 20th Euro-Par International Workshops in EURO-PAR 2014: PARALLEL PROCESSING WORKSHOPS, PT II, VOLUME: 8806
INDEXED IN: Scopus WOS DBLP CrossRef: 7
IN MY: ORCID | DBLP
63
TITLE: Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs  Full Text
AUTHORS: Tiago Dias; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING, VOLUME: 2014, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
64
TITLE: A Compact and Scalable RNS Architecture  Full Text
AUTHORS: Pedro Miguens Matutino; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in PROCEEDINGS OF THE 2013 IEEE 24TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 13)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
65
TITLE: A comparison of computing architectures and parallelization frameworks based on a two-dimensional FDTD
AUTHORS: Kuan, L; Tomas, P ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013 in Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
INDEXED IN: Scopus DBLP CrossRef: 2
IN MY: ORCID | DBLP
66
TITLE: A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems  Full Text
AUTHORS: Leonel Sousa ; Samuel Antao; Jose Germano ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON EDUCATION, VOLUME: 56, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID | DBLP
67
TITLE: Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines
AUTHORS: Frederico Pratas; Diego Oriato; Oliver Pell; Ricardo A Mata; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) in 2013 IEEE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
68
TITLE: AN RNS-BASED ARCHITECTURE TARGETING HARDWARE ACCELERATORS FOR MODULAR ARITHMETIC
AUTHORS: Samuel Antao; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) in 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
69
TITLE: DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
AUTHORS: Ambrose, JA; Pettenghi, H ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | DBLP
70
TITLE: High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs
AUTHORS: Dias, T; Roma, N ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013 in Conference on Design and Architectures for Signal and Image Processing, DASIP
INDEXED IN: Scopus DBLP
IN MY: ORCID | DBLP
Page 7 of 29. Total results: 283.

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