ProfileOfResearchers

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TITLE: Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model
AUTHORS: Diogo Antão; Luís Taniça; Aleksandar Ilic; Frederico Pratas; Pedro Tomás ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: Parallel Processing and Applied Mathematics - 10th International Conference, PPAM 2013, Warsaw, Poland, September 8-11, 2013, Revised Selected Papers, Part I, VOLUME: 8384

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CrossRef: 4

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TITLE: Multi-level Parallelization of Advanced Video Coding on Hybrid CPU plus GPU Platforms
AUTHORS: Svetislav Momcilovic; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: 18th International Conference on Euro-Par Parallel Processing in EURO-PAR 2012: PARALLEL PROCESSING WORKSHOPS, VOLUME: 7640

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TITLE: On the Design of RNS Reverse Converters for the Four-Moduli Set {2(n)+1, 2(n)-1, 2(n), 2(n+1)+1} Full Text
AUTHORS: Leonel Sousa ; Samuel Antao; Ricardo Chaves ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 21, ISSUE: 10

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TITLE: Open the Gates: Using High-level Synthesis Towards Programmable LDPC Decoders on FPGAs
AUTHORS: Pratas, F; Andrade, J; Falcao, G ; Silva, V; Sousa, L ;
PUBLISHED: 2013, SOURCE: IEEE Global Conference on Signal and Information Processing (GlobalSIP) in 2013 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP)

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TITLE: Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks
AUTHORS: Jude Angelo Ambrose; Hector Pettenghi ; Darshana Jayasinghe; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IET CIRCUITS DEVICES & SYSTEMS, VOLUME: 7, ISSUE: 5

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TITLE: RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 60, ISSUE: 6

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TITLE: Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems Full Text
AUTHORS: Tiago Dias; Sebastian Lopez; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 41, ISSUE: 2

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TITLE: Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters
AUTHORS: Falcao, G ; Andrade, J; Silva, V; Yamagiwa, S; Sousa, L ;
PUBLISHED: 2013, SOURCE: 10th IEEE International Symposium on Wireless Communication Systems 2013, ISWCS 2013 in Proceedings of the International Symposium on Wireless Communication Systems

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TITLE: Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters
AUTHORS: Gabriel Falcão Paiva Fernandes; Joao Andrade; Vítor Manuel Mendes da Silva; Shinichi Yamagiwa; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: ISWCS 2013, The Tenth International Symposium on Wireless Communication Systems, Ilmenau, TU Ilmenau, Germany, August 27-30, 2013

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