Mário Pereira Véstias
AuthID: R-000-CZ3
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TITLE: Decimal multiplication in FPGA with a novel decimal adder/subtractor
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2021, SOURCE: Algorithms, VOLUME: 14, ISSUE: 7
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2021, SOURCE: Algorithms, VOLUME: 14, ISSUE: 7
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TITLE: Implementing CNNs Using a Linear Array of Full Mesh CGRAs
AUTHORS: Mário, V; Lopes, JD; Véstias, M; de Sousa, JT;
PUBLISHED: 2020, SOURCE: 16th International Symposium on Applied Reconfigurable Computing, ARC 2020 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 12083 LNCS
AUTHORS: Mário, V; Lopes, JD; Véstias, M; de Sousa, JT;
PUBLISHED: 2020, SOURCE: 16th International Symposium on Applied Reconfigurable Computing, ARC 2020 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 12083 LNCS
23
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs Full Text
AUTHORS: Véstias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Microprocessors and Microsystems, VOLUME: 77
AUTHORS: Véstias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Microprocessors and Microsystems, VOLUME: 77
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TITLE: Processing systems for deep learning inference on edge devices
AUTHORS: Véstias, M;
PUBLISHED: 2020, SOURCE: Internet of Things
AUTHORS: Véstias, M;
PUBLISHED: 2020, SOURCE: Internet of Things
25
TITLE: Moving deep learning to the edge Full Text
AUTHORS: Véstias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Algorithms, VOLUME: 13, ISSUE: 5
AUTHORS: Véstias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Algorithms, VOLUME: 13, ISSUE: 5
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TITLE: A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs
AUTHORS: Vestias, MP; Duarte, RP; De Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
AUTHORS: Vestias, MP; Duarte, RP; De Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
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TITLE: Hyperspectral Compressive Sensing With a System-On-Chip FPGA
AUTHORS: Nascimento, JMP; Vestias, MP; Martin, G;
PUBLISHED: 2020, SOURCE: IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING, VOLUME: 13
AUTHORS: Nascimento, JMP; Vestias, MP; Martin, G;
PUBLISHED: 2020, SOURCE: IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING, VOLUME: 13
28
TITLE: Moving Deep Learning to the Edge Full Text
AUTHORS: Vestias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: ALGORITHMS, VOLUME: 13, ISSUE: 5
AUTHORS: Vestias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: ALGORITHMS, VOLUME: 13, ISSUE: 5
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ORCID29
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs Full Text
AUTHORS: Vestias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 77
AUTHORS: Vestias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 77
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID30
TITLE: Efficient Design of Pruned Convolutional Neural Networks on FPGA
AUTHORS: Véstias, M;
PUBLISHED: 2020, SOURCE: Journal of Signal Processing Systems, VOLUME: 93, ISSUE: 5
AUTHORS: Véstias, M;
PUBLISHED: 2020, SOURCE: Journal of Signal Processing Systems, VOLUME: 93, ISSUE: 5
