Horácio Cláudio de Campos Neto


AuthID: R-000-5ZS

Confirmed Publications: 40



1
TITLE: Design of a Massively Parallel Computing Architecture for Dense Matrix Multiplication
AUTHORS: Wilson Jose; Ana Rita Silva; Mario Vestias ; Horacio Neto ;
PUBLISHED: 2013, SOURCE: IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) in 2013 IEEE 4TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
2
TITLE: Design of a Multiband Full-Rate Ultra-Wideband Receiver in FPGA
AUTHORS: Mario Vestias ; Horacio Neto ; Helena Sarmento ;
PUBLISHED: 2013, SOURCE: IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) in 2013 IEEE 4TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
3
TITLE: A High-Performance Reconfigurable Computing Architecture using a Magnetic Configuration Memory
AUTHORS: Victor Silva; Jorge R Fernandes ; Mario P Vestias ; Horacio C Neto ;
PUBLISHED: 2012, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2012 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID
4
TITLE: Design of high-speed viterbi decoders on virtex-6 FPGAs
AUTHORS: Vestias, M ; Neto, H ; Sarmento, H ;
PUBLISHED: 2012, SOURCE: 15th Euromicro Conference on Digital System Design, DSD 2012 in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
INDEXED IN: Scopus CrossRef
IN MY: ORCID
5
TITLE: Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions
AUTHORS: Silva, V; Vestias, MP ; Neto, HC ; Fernandes, JR ;
PUBLISHED: 2012, SOURCE: 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012 in 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
INDEXED IN: Scopus CrossRef
IN MY: ORCID
6
TITLE: Parallel decimal multipliers and squarers using Karatsuba-Ofman's algorithm
AUTHORS: Vestias, M ; Neto, H ;
PUBLISHED: 2012, SOURCE: 15th Euromicro Conference on Digital System Design, DSD 2012 in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012
INDEXED IN: Scopus CrossRef
IN MY: ORCID
7
TITLE: Sliding block Viterbi decoders in FPGA
AUTHORS: Vestias, M ; Neto, H ; Sarmento, H ;
PUBLISHED: 2012, SOURCE: 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
INDEXED IN: Scopus CrossRef
IN MY: ORCID
8
TITLE: A dynamic buffer resize technique for networks-on-chip on FPGA
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
9
TITLE: Iterative decimal multiplication using binary arithmetic
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
10
TITLE: Revisiting the Newton-Raphson iterative method for decimal division
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 21st International Conference on Field Programmable Logic and Applications, FPL 2011 in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID
Page 1 of 4. Total results: 40.

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