Mário Pereira Véstias
AuthID: R-000-CZ3
51
TITLE: Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs
AUTHORS: Vestias, M; Duarte, RP; de Sousa, JT; Neto, H;
PUBLISHED: 2018, SOURCE: 28th International Conference on Field Programmable Logic and Applications (FPL) in 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Vestias, M; Duarte, RP; de Sousa, JT; Neto, H;
PUBLISHED: 2018, SOURCE: 28th International Conference on Field Programmable Logic and Applications (FPL) in 2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
52
TITLE: Improving the area of fast parallel decimal multipliers
AUTHORS: Vestias, M; Neto, H;
PUBLISHED: 2018, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 61
AUTHORS: Vestias, M; Neto, H;
PUBLISHED: 2018, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 61
53
TITLE: High-Performance Reconfigurable Computing
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
54
TITLE: Adaptive Networks for On-Chip Communication
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
55
TITLE: Decimal Hardware Multiplier
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
AUTHORS: Mário Pereira Vestias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
56
TITLE: Viterbi Decoder in Hardware
AUTHORS: Mário Pereira Véstias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
AUTHORS: Mário Pereira Véstias;
PUBLISHED: 2018, SOURCE: Encyclopedia of Information Science and Technology, Fourth Edition
57
TITLE: Stochastic theater: stochastic datapath generation framework for fault-tolerant IoT sensors
AUTHORS: Rui P Duarte; Mário Véstias; Carlos Carvalho; João Casaleiro;
PUBLISHED: 2018, SOURCE: i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers, VOLUME: 4, ISSUE: 1
AUTHORS: Rui P Duarte; Mário Véstias; Carlos Carvalho; João Casaleiro;
PUBLISHED: 2018, SOURCE: i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers, VOLUME: 4, ISSUE: 1
INDEXED IN: 
Handle
Handle58
TITLE: Decimal addition on FPGA based on a mixed BCD/excess-6 representation Full Text
AUTHORS: Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 55
AUTHORS: Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 55
59
TITLE: K-means clustering on CGRA
AUTHORS: Lopes, JD; De Sousa, JT; Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
AUTHORS: Lopes, JD; De Sousa, JT; Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
60
TITLE: Parallel dot-products for deep learning on FPGA
AUTHORS: Vestias, M; Duarte, RP; De Sousa, JT; Neto, H;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
AUTHORS: Vestias, M; Duarte, RP; De Sousa, JT; Neto, H;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications, FPL 2017 in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
