Mário Pereira Véstias
AuthID: R-000-CZ3
61
TITLE: K-means clustering on CGRA
AUTHORS: Lopes, JD; de Sousa, JT; Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Lopes, JD; de Sousa, JT; Neto, H; Vestias, M;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
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ORCID
ORCID62
TITLE: Parallel Dot-Products for Deep Learning on FPGA
AUTHORS: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLISHED: 2017, SOURCE: 27th International Conference on Field Programmable Logic and Applications (FPL) in 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: WOS
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ORCID63
TITLE: System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing
AUTHORS: Jose M P Nascimento; Mario Vestias;
PUBLISHED: 2016, SOURCE: JOURNAL OF APPLIED REMOTE SENSING, VOLUME: 10, ISSUE: 1
AUTHORS: Jose M P Nascimento; Mario Vestias;
PUBLISHED: 2016, SOURCE: JOURNAL OF APPLIED REMOTE SENSING, VOLUME: 10, ISSUE: 1
64
TITLE: Multi-core for K-means clustering on FPGA
AUTHORS: Canilho, J; Véstias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
AUTHORS: Canilho, J; Véstias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications, FPL 2016 in FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications
65
TITLE: Multi-Core for K-Means Clustering on FPGA
AUTHORS: Canilho, J; Vestias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
AUTHORS: Canilho, J; Vestias, M; Neto, H;
PUBLISHED: 2016, SOURCE: 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
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ORCID66
TITLE: XtokaxtikoX: A Stochastic Computing-Based Autonomous Cyber-Physical System
AUTHORS: Duarte, RP; Neto, H; Vestias, M;
PUBLISHED: 2016, SOURCE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
AUTHORS: Duarte, RP; Neto, H; Vestias, M;
PUBLISHED: 2016, SOURCE: IEEE International Conference on Rebooting Computing (ICRC) in 2016 IEEE INTERNATIONAL CONFERENCE ON REBOOTING COMPUTING (ICRC)
67
TITLE: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTHORS: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLISHED: 2015, SOURCE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, ISSUE: 1
AUTHORS: Jose, WM; Silva, AR; Vestias, MP; Neto, HC;
PUBLISHED: 2015, SOURCE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 82, ISSUE: 1
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ORCID68
TITLE: A Many-Core Co-Processor for Embedded Parallel Computing on FPGA
AUTHORS: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTHORS: Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
69
TITLE: Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture
AUTHORS: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTHORS: Joao Pinhao; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
70
TITLE: Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA
AUTHORS: Tiago Rodrigues; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
AUTHORS: Tiago Rodrigues; Mario Vestias;
PUBLISHED: 2015, SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
