Andreas Veneris
AuthID: R-00G-7GJ
1
TITLE: Automated Design Debugging With Maximum Satisfiability Full Text
AUTHORS: Chen, YB; Safarpour, S; Marques Silva, J ; Veneris, A;
PUBLISHED: 2010, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 29, ISSUE: 11
AUTHORS: Chen, YB; Safarpour, S; Marques Silva, J ; Veneris, A;
PUBLISHED: 2010, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 29, ISSUE: 11
2
TITLE: Spatial and temporal design debug using partial MaxSAT
AUTHORS: Yibin Chen; Sean Safarpour; Andreas G Veneris; João P Marques Silva ;
PUBLISHED: 2009, SOURCE: 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 in Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
AUTHORS: Yibin Chen; Sean Safarpour; Andreas G Veneris; João P Marques Silva ;
PUBLISHED: 2009, SOURCE: 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 in Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
